Discussion:
B: Sun Ultra60, Sun U420R
(zu alt für eine Antwort)
Gert Doering
2019-11-16 11:45:24 UTC
Permalink
Moin,

ich hab hier ein paar Sun-Schätzchen, die ein neues Zuhause suchen.
Platzgründe...

- 1x Ultra60 (2x 450 MHz, 2G RAM, NVRAM platt)
- 1x U420R (4x 450 MHz, 4G RAM [2G onboard + 2G auf riser-card])
- 1x Sun-Storage externes U2W-Gehäuse für 12 Platten inkl. Rahmen
(auf ebay grad für 250 EUR zu finden...)
- ca. 5x 18G U2W-Platten im SUN-Rahmen

OBP-Output von der U60 hängt unten, die U420R steht noch im RZ, kann ich
bei Interesse einholen.

Die Maschinen "gegen Abholung in München", bei Gehäuse und Platten lass
ich über Porto & Aufwand mit mir reden.

Müssen raus... wenn sie keiner will, blutenden Herzens am 2.1. auf den
Wertstoffhof.

gert
------------------------------------------
Hardware Power ON
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000ÿ
Button Power ON
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000

Probing keyboard Done
%o0 = 0000.0000.0055.4001

Executing Power On SelfTest

0>
0>@(#) Sun Ultra 60(UltraSPARC-II 2-way) UPA/PCI POST 2.0.2 10/19/1998 10:46 AM
0>INFO: Processor 0 is master.
0>
0> <00> Init System BSS
0> <00> NVRAM Battery Detect Test
0>STATUS =FAILED
0>TEST =NVRAM Battery Detect
TTF =0
PASSES =1
ERRORS =1
SUSPECT=NVRAM U2706
0>MESSAGE=NVRAM Low Battery
addr 000001ff.f1001ff0
exp 00
obs 10
0> <00> DMMU TLB Tag Access Test
0> <00> DMMU TLB RAM Access Test
0> <00> IMMU TLB Tag Access Test
0> <00> IMMU TLB RAM Access Test
0> <00> Probe Ecache
0>INFO: CPU 450 MHz: 4096KB Ecache
0> <00> Ecache RAM Addr Test
0> <00> Ecache Tag Addr Test
0> <00> Ecache Tag Test
0> <00> Invalidate Ecache Tags
0>INFO: Processor 2 - UltraSPARC-II.
0> <00> Init SC Regs
0> <00> SC Address Reg Test
0> <00> SC Reg Index Test
0> <00> SC Regs Test
0> <00> SC Dtag RAM Addr Test
0> <00> SC Cache Size Init
0> <00> SC Dtag RAM Data Test
0> <00> SC Dtag Init
0> <00> Probe Memory
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Malloc Post Memory
0> <00> Init Post Memory
0> <00> Post Memory Addr Test
0> <00> Map PROM/STACK/NVRAM in DMMU
0> <00> Memory Stack Test
0> ERROR: CPU Slave 2 Timeout
0> WARNING: Unable to dispatch Int to mid 00000002
0> WARNING: Unable to dispatch Int to mid 00000002
0> WARNING: Unable to dispatch Int to mid 00000002
0> <00> DMMU Hit/Miss Test
0> <00> IMMU Hit/Miss Test
0> <00> DMMU Little Endian Test
0> <00> IU ASI Access Test
0> <00> FPU ASI Access Test
0> <1f> Init Psycho
0> <1f> PIO Read Error, Master Abort Test
0> <1f> PIO Read Error, Target Abort Test
0> <1f> PIO Write Error, Master Abort Test
0> <1f> PIO Write Error, Target Abort Test
0> <1f> Timer Increment Test
0> <00> Copy Post to Memory
0> <00> Ecache Thrash Test
0> <00> Init Memory
0> <00> Memory Addr w/ Ecache Test
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Block Memory Addr Test
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> ECC Memory Addr Test
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Memory Status Test
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> V9 Instruction Test
0> <00> CPU Tick and Tick Compare Reg Test
0> <00> CPU Soft Trap Test
0> <00> CPU Softint Reg and Int Test
0> <1f> Init Psycho
0> <1f> Psycho Cntl and UPA Reg Test
0> <1f> Psycho DMA Scoreboard Reg Test
0> <1f> Psycho Perf Cntl Reg Test
0> <1f> PIO Decoder and BCT Test
0> <1f> PCI Byte Enable Test
0> <1f> Counter/Timer Limit Regs Test
0> <1f> Timer Reload Test
0> <1f> Timer Periodic Test
0> <1f> Mondo Int Map (short) Reg Test
0> <1f> Mondo Int Set/Clr Reg Test
0> <1f> Psycho IOMMU Regs Test
0> <1f> Psycho IOMMU RAM Address Test
0> <1f> Psycho IOMMU CAM Address Test
0> <1f> IOMMU TLB Compare Test
0> <1f> IOMMU TLB Flush Test
0> <1f> Stream Buff A Control Reg Test
0> <1f> Psycho ScacheA Page Tag Addr Test
0> <1f> Psycho ScacheA Line Tag Addr Test
0> <1f> Psycho ScacheA RAM Addr Test
0> <1f> Psycho ScacheA Error Status NTA Test
0> <1f> Psycho ScacheB Page Tag Addr Test
0> <1f> Psycho ScacheB Line Tag Addr Test
0> <1f> Psycho ScacheB RAM Addr Test
0> <1f> Psycho ScacheB Error Status NTA Test
0> <1f> PBMA PCI Config Space Regs Test
0> <1f> PBMA Control/Status Reg Test
0> <1f> PBMA Diag Reg Test
0> <1f> PBMB PCI Config Space Regs Test
0> <1f> PBMB Control/Status Reg Test
0> <1f> PBMB Diag Reg Test
0> <00> FPU Regs Test
0> <00> FPU Move Regs Test
0> <00> FPU State Reg Test
0> <00> FPU Functional Test
0> <00> FPU Trap Test
0> <00> DMMU Primary Context Reg Test
0> <00> DMMU Secondary Context Reg Test
0> <00> DMMU TSB Reg Test
0> <00> DMMU Tag Access Reg Test
0> <00> DMMU VA Watchpoint Reg Test
0> <00> DMMU PA Watchpoint Reg Test
0> <00> IMMU TSB Reg Test
0> <00> IMMU Tag Access Reg Test
0> <00> DMMU TLB Tag Access Test
0> <00> DMMU TLB RAM Access Test
0> <00> Dcache RAM Test
0> <00> Dcache Tag Test
0> <00> Icache RAM Test
0> <00> Icache Tag Test
0> <00> Icache Next Test
0> <00> Icache Predecode Test
0> <00> CPU Addr Align Trap Test
0> <00> DMMU Access Priv Page Test
0> <00> DMMU Write Protected Page Test
0> <1f> Init Psycho
0> <1f> Pri CE ECC Error Test
0> <1f> Pri UE ECC Error Test
0> <1f> Pri 2 bit w/ bit hole UE ECC Err Test
0> <1f> Pri 3 bit UE ECC Err Test
0> <1f> Streaming DMA UE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Lpbk Test
0> <1f> Consistent DMA UE ECC Rd Error Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Lpbk Test
0> <1f> Consistent DMA CE ECC Rd Err Ebus Test
0> <1f> Consistent DMA CE ECC Rd Err Lpbk Test
0> <1f> Consistent DMA CE ECC R/M/W Err Ebus Test
0> <1f> Consistent DMA CE ECC R/M/W Err Lpbk Test
0> <1f> Consistent DMA Wr Data Parity Err Lpbk Test
0> <1f> Pass-Thru DMA UE ECC Rd Err Ebus Test
0> <1f> Pass-Thru DMA UE ECC R/M/W Err Ebus Test
0> <1f> Pass-Thru DMA UE ECC R/M/W Err Lpbk Test
0> <1f> Pass-Thru DMA CE ECC Rd Err Ebus Test
0> <1f> Pass-Thru DMA CE ECC Rd Err Lpbk Test
0> <1f> Pass-Thru DMA CE ECC R/M/W Err Ebus Test
0> <1f> Pass-Thru DMA CE ECC R/M/W Err Lpbk Test
0> <1f> Pass-Thru DMA Write Data Parity Err, Lpbk Test
0> <1f> Init Psycho
0> <1f> Mondo Generate Interrupt Test
0> <1f> Timer Interrupt Test
0> <1f> Timer Interrupt w/ periodic Test
0> <1f> Psycho Stream Buff A Flush Sync Test
0> <1f> Psycho Stream Buff B Flush Sync Test
0> <1f> Psycho Stream Buff A Flush Invalidate Test
0> <1f> Psycho Stream Buff B Flush Invalidate Test
0> <1f> Psycho Merge Buffer w/ Scache A Test
0> <1f> Psycho Merge Buffer w/ Scache B Test
0> <1f> Consist DMA Rd, IOMMU miss Ebus Test
0> <1f> Consist DMA Rd, IOMMU miss Lpbk Test
0> <1f> Consist DMA Rd, IOMMU hit Ebus Test
0> <1f> Consist DMA Rd, IOMMU hit Lpbk Test
0> <1f> Consist DMA Wr, IOMMU miss Ebus Test
0> <1f> Consist DMA Wr, IOMMU miss Lpbk Test
0> <1f> Consist DMA Wr, IOMMU hit Ebus Test
0> <1f> Consist DMA Wr, IOMMU hit Lpbk Test
0> <1f> Stream DMA Rd, IOMMU miss, Scache Miss Ebus Test
0> <1f> Stream DMA Rd, IOMMU miss, Scache Miss Lpbk Test
0> <1f> Stream DMA Rd, IOMMU hit, Scache Miss Ebus Test
0> <1f> Stream DMA Rd, IOMMU hit, Scache Miss Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit (prev rd) Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit Ebus Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit (prev rd) Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit(prev wr) Ebus Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache Hit (prev wr) Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit(prev wr) Ebus Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache Hit (prev wr) Lpbk Test
0> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Ebus Test
0> <1f> Stream DMA Wr, IOMMU miss, Scache Miss Lpbk Test
0> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Ebus Test
0> <1f> Stream DMA Wr, IOMMU hit, Scache Miss Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev rd) Hit Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev rd) Hit Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache(prev wr) Hit Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache(prev wr) Hit Lpbk Test
0> <1f> Pass-Thru DMA Rd, Ebus device Test
0> <1f> Pass-Thru DMA Rd, Loopback Mode Test
0> <1f> Pass-Thru DMA Wr, Ebus device Test
0> <1f> Pass-Thru DMA Wr, Loopback Mode Test
0> <1f> Consist DMA Rd, IOMMU LRU Lock Ebus Test
0> <1f> Consist DMA Rd, IOMMU LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU miss, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Rd, IOMMU Miss, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Rd, IOMMU Hit, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Ebus Test
0> <1f> Stream DMA Rd, IOMMU LRU Lock, Scache Miss Lpbk Test
0> <1f> Consist DMA Wr, IOMMU LRU Locked Ebus Test
0> <1f> Consist DMA Wr, IOMMU LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Wr, IOMMU Miss, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Ebus Test
0> <1f> Stream DMA Wr, IOMMU Hit, Scache LRU Lock Lpbk Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Ebus Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache Miss Lpbk Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache(prev rd) Hit Ebus Test
0> <1f> Stream DMA Wr, IOMMU LRU Lock, Scache(prev rd) Hit Lpbk Test
0> <00> Init Memory
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Memory w/ Ecache Test
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> Block Memory Test
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> ECC Blk Memory Test
0>INFO: 512MB Bank 0
0>INFO: 512MB Bank 1
0>INFO: 512MB Bank 2
0>INFO: 512MB Bank 3
0> <00> UltraSPARC-2 Prefetch Instructions Test
0> <00> Test 0: prefetch_mr
0> <00> Test 1: prefetch to non-cacheable page
0> <00> Test 2: prefetch to page with dmmu misss
0> <00> Test 3: prefetch miss does not check alignment
0> <00> Test 4: prefetcha with asi 0x4c is noped
0> <00> Test 5: prefetcha with asi 0x54 is noped
0> <00> Test 6: prefetcha with asi 0x6e is noped
0> <00> Test 7: prefetcha with asi 0x76 is noped
0> <00> Test 8: prefetch with fcn 5
0> <00> Test 9: prefetch with fcn 2
0> <00> Test 10: prefetch with fcn 12
0> <00> Test 11: prefetch with fcn 16 is noped
0> <00> Test 12: prefetch with fcn 29 is noped
0> <00> Test 13: prefetcha with asi 0x15 is noped
0> <00> Test 14: prefetch with fcn 3
0> <00> Test 15: prefetcha14 with fcn 2
0> <00> Test 16: prefetcha80_mr
0> <00> Test 17: prefetcha81_1r
0> <00> Test 18: prefetcha10_mw
0> <00> Test 19: prefetcha80_17 is noped
0> <00> Test 20: prefetcha10_6: illegal instruction trap
0> <00> Test 21: prefetcha11_1w
0> <00> Test 22: prefetcha81_31
0> <00> Test 23: prefetcha11_15: illegal instruction trap
0>STATUS =FAILED : First failing device is NVRAM U2706.


Power On Selftest Completed
ß Status = 0000.0000.0000.0001 ffff.ffff.f00b.3818 ff9d.ffff.0bd1.e111
Software Power ON
Master CPU online
Master Version: 0000.0000.1700.11a0
Slave Version: 0000.0000.1700.11a0
CPU E$ (M) 0000.0000.0040.0000 (S) 0000.0000.0040.0000

@(#) UPA/PCI 3.23 Version 1 created 1999/07/16 12:08
Clearing DTAGS Done
Probing Memory Done
MEM BASE = 0000.0000.a000.0000
MEM SIZE = 0000.0000.2000.0000
MMUs ON
Copy Done
PC = 0000.01ff.f000.2800
PC = 0000.0000.0000.2844
Decompressing into Memory Done
Size = 0000.0000.0006.eb80
ttya initialized
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing Memory Bank #0 128 128 128 128 : 512 Megabytes
Probing Memory Bank #1 128 128 128 128 : 512 Megabytes
Probing Memory Bank #2 128 128 128 128 : 512 Megabytes
Probing Memory Bank #3 128 128 128 128 : 512 Megabytes
Probing Floppy: No drives detected
Probing EBUS SUNW,CS4231
Probing UPA Slot at 1e,0 SUNW,ffb
Probing UPA Slot at 1d,0 Nothing there
Probing /***@1f,4000 at Device 1 pci108e,1000 network
Probing /***@1f,4000 at Device 3 scsi disk tape scsi disk tape
Probing /***@1f,4000 at Device 2 Nothing there
Probing /***@1f,4000 at Device 4 Nothing there
Probing /***@1f,4000 at Device 5 Nothing there
Probing /***@1f,2000 at Device 1 Nothing there
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Starting real time clock...
Incorrect configuration checksum;
Setting NVRAM parameters to default values.
Setting diag-switch? NVRAM parameter to true
Probing Memory Bank #0 128 128 128 128 : 512 Megabytes
Probing Memory Bank #1 128 128 128 128 : 512 Megabytes
Probing Memory Bank #2 128 128 128 128 : 512 Megabytes
Probing Memory Bank #3 128 128 128 128 : 512 Megabytes
Probing Floppy: No drives detected
Probing EBUS SUNW,CS4231
Probing UPA Slot at 1e,0 SUNW,ffb
Probing UPA Slot at 1d,0 Nothing there
Probing /***@1f,4000 at Device 1 pci108e,1000 network
Probing /***@1f,4000 at Device 3 scsi disk tape scsi disk tape
Probing /***@1f,4000 at Device 2 Nothing there
Probing /***@1f,4000 at Device 4 Nothing there
Probing /***@1f,4000 at Device 5 Nothing there
Probing /***@1f,2000 at Device 1 Nothing there

(2 X UltraSPARC-II 450MHz), No Keyboard
OpenBoot 3.23, 2048 MB memory installed, Serial #16777215.
Ethernet address ff:ff:ff:ff:ff:ff, Host ID: ffffffff.


The IDPROM contents are invalid

Initializing 1023 megs of memory at addr 80000000 581
Power On Self Test Failed. Cause: NVRAM U2706
{0} ok
::wq
{0} ok probe-scsi
Target 1
Unit 0 Disk FUJITSU MAG3182L SUN18G 1111
Target 6
Unit 0 Removable Read Only device TOSHIBA DVD-ROM SD-M14011009

{0} ok boot disk1
Boot device: /***@1f,4000/***@3/***@1,0 File and args:
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
FCode UFS Reader 1.12 00/07/17 15:48:16.
Loading: /platform/SUNW,Ultra-60/ufsboot
Loading: /platform/sun4u/ufsboot
SunOS Release 5.10 Version Generic_118833-33 64-bit
Copyright 1983-2006 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Invalid format code in IDprom.
WARNING: Time-of-day chip had incorrect date; check and reset.
--
USENET is *not* the non-clickable part of WWW!
//www.muc.de/~gert/
Gert Doering - Munich, Germany ***@greenie.muc.de
fax: +49-89-35655025 ***@net.informatik.tu-muenchen.de
Gert Doering
2019-11-18 16:46:38 UTC
Permalink
Post by Gert Doering
- 1x Ultra60 (2x 450 MHz, 2G RAM, NVRAM platt)
- 1x U420R (4x 450 MHz, 4G RAM [2G onboard + 2G auf riser-card])
Die U60 ist vergeben.

Die U420R hab ich heute besucht, OBP-Output hängt an...

gert
----
{0} ok setenv diag-switch? truee
diag-switch? = true
{0} ok reset
Resetting ...


Software Power ON
Master CPU : 0000.0000.0055.11a0
Slave CPU : 0000.0001.0055.11a0
Slave CPU : 0000.0002.0055.11a0
Slave CPU : 0000.0003.0055.11a0
Master E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000
Slave E$ : 0000.0000.0040.0000

@(#) UPA/PCI 3.23 Version 0 created 1999/06/30 13:53
Clearing DTAGS Done
Probing Memory
CONFIG = 0000.0000.1010.1010
MEM BASE = 0000.0000.0000.0000
MEM SIZE = 0000.0001.0000.0000
MMUs ON
Copy Done
PC = 0000.01ff.f000.2a50
PC = 0000.0000.0000.2a94
Decompressing into Memory Done
Size = 0000.0000.0006.ef90
ttya initialized
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Probing Memory Bank #0 1 1 1 1 : 4 Gigabytes
Probing Floppy: No drives detected
Probing EBUS Nothing there
Probing UPA Slot at 1e,0 Nothing there
Probing UPA Slot at 1d,0 Nothing there
Probing /***@1f,4000 at Device 1 pci108e,1000 network
Probing /***@1f,4000 at Device 3 scsi disk tape scsi disk tape
Probing /***@1f,4000 at Device 2 Nothing there
Probing /***@1f,4000 at Device 4 usb usb
Probing /***@1f,4000 at Device 5 TSI,gfxp
Probing /***@1f,2000 at Device 1 firewire
SC Control: EWP:0 IAP:0 FATAL:0 WAKEUP:0 BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
Probing Memory Bank #0 1 1 1 1 : 4 Gigabytes
Probing Floppy: No drives detected
Probing EBUS Nothing there
Probing UPA Slot at 1e,0 Nothing there
Probing UPA Slot at 1d,0 Nothing there
Probing /***@1f,4000 at Device 1 pci108e,1000 network
Probing /***@1f,4000 at Device 3 scsi disk tape scsi disk tape
Probing /***@1f,4000 at Device 2 Nothing there
Probing /***@1f,4000 at Device 4 usb usb
Probing /***@1f,4000 at Device 5 TSI,gfxp
Probing /***@1f,2000 at Device 1 firewire

Sun Enterprise 420R (4 X UltraSPARC-II 450MHz), No Keyboard
OpenBoot 3.23, 4096 MB memory installed, Serial #16665554.
Ethernet address 8:0:20:fe:4b:d2, Host ID: 80fe4bd2.



Initializing 1 megs of memory at addr fff00000 0
Initializing 4095 megs of memory at addr 0 4094 ...

Using Onboard Transceiver - Timeout waiting for AutoNegotiation Status to be updated.
Timeout reading Link status. Check cable and try again.
Timeout waiting for AutoNegotiation Status to be updated.
Timeout reading Link status. Check cable and try again.
Timeout waiting for AutoNegotiation Status to be updated.
Timeout reading Link status. Check cable and try again.
AutoNegotiation Timeout.
Check Cable or Contact your System Administrator.
Link Down.
Setting up Network Link and Speed.
Using Onboard Transceiver - Timeout waiting for AutoNegotiation Status to be updated.
...
--
USENET is *not* the non-clickable part of WWW!
//www.muc.de/~gert/
Gert Doering - Munich, Germany ***@greenie.muc.de
fax: +49-89-35655025 ***@net.informatik.tu-muenchen.de
Gerrit Heitsch
2019-11-18 17:03:52 UTC
Permalink
Post by Gert Doering
Post by Gert Doering
- 1x Ultra60 (2x 450 MHz, 2G RAM, NVRAM platt)
- 1x U420R (4x 450 MHz, 4G RAM [2G onboard + 2G auf riser-card])
Die U60 ist vergeben.
Die U420R hab ich heute besucht, OBP-Output hängt an...
Ich würde da noch mal schnell '.idprom' eingeben und mir die Ausgabe
wegsichern. Die brauchst du wenn das NVRAM den Geist aufgibt und du ein
neues, leeres mit den nötigen Daten befüllen willst.

Gerrit

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